1. Field of the Invention
The present invention relates to a magnetic recording/reproducing apparatus and, more particularly, to an improvement of a data reproducing circuit incorporated in this magnetic recording/reproducing apparatus.
2. Description of the Related Art
A conventional magnetic recording/reproducing apparatus such, as a hard disc drive (HDD), etc. is provided with a data reproducing circuit for reproducing data from signals read from a recording medium by a magnetic head. This data reproducing circuit generates read data pulses including clock pulses from signals read by the magnetic head. The data reproducing circuit further includes a separator circuit which separates data pulses, and a decoder circuit which decodes the data pulses to reproduced data.
A data reproducing circuit as shown in FIG. 1 is known as a circuit for generating a read data pulse RD. That is, a signal read from a recording medium 10 by a head 1 is amplified by a pre-amplifier 2. The amplified read signal is further amplified to a fixed level by an AGC (Automatic Gain Control) amplifier 3. The frequency range of the output signal from the AGC amplifier 3 is restricted by a low pass filter (LPF) 4. A low frequency components of the output signal from the AGC amplifier 3 only passes through the LPF 4 and is input to a binarization circuit 5.
The output signal from the LPF 4 is also input to a full wave rectification circuit 6. The full wave rectification circuit 6 rectifies the full wave of signal read from the LPF 4. The full wave rectified output signal FWR is input to an AGC signal generator 7 and an integrating circuit 8, The integrating circuit 8 includes a capacitor and smoothes the rectified output signal FWR. The AGC signal generator 7 generates an AGC signal by comparing the FWR signal with a reference signal and sends the AGC signal to the AGC amplifier 3 so that the output of the AGC amplifier 3 is kept at a fixed voltage level.
The integrating circuit 8 generates a threshold signal TH required for the operation of the binarization circuit 5 by integrating the full wave rectified signal FWR, The binarization circuit 5 has a differentiating circuit (not shown) for differentiating the output signal RS from the LPF 4 and a window generating circuit (not shown) for generating a window by a threshold signal TH. The window generating circuit compares the level of the output signal RS from the LPF 4 with that of the threshold signal TH and generates window pulses having duration equivalent to a period when the level of the signal RS is higher than the level of the threshold signal (+TH or is lower than the level of an inverted threshold signal -TH).
The binarization circuit 5 has a pulse generating circuit (not shown) having a comparator for detecting the zero crossing point of differentiated signal from the differentiating circuit. This pulse generating circuit reads data pulses RD, synchronizing with the zero crossing point of the differentiated signal, if the zero cross point is detected by the comparator when the window pulses exist.
At the time of the data recording (writing), the head 1 executes the write operation on a recording medium (disc) according to write data. Therefore, there is no read signal from the head 1 and the output from the pre-amplifier 2 will become zero. At this time, the AGC signal generator 7 fixes (holds) the gain of the AGC amplifier 3 according to a write gate signal (a write control signal) WG that is output from an HDD controller 9 to prevent increase of gain. The controller 9 generates the WG signal when a host system, such as a personal computer, sends a write command to the controller.
However, the integrating circuit 8 keep functioning at the time of the writing. As shown in FIG. 2, there is no RS signal from LPF 4 during the write operation (i.e. when the signal WG is ON). If the period of the write operation is relatively long, the voltage of the output signal TH of the integrating circuit 6 will drop to the bias voltage level. Accordingly, when the write operation is completed and the reproducing operation again begins, a time based on the time constant of the integrating circuit 8 is required for the voltage level of the signal TH to go up to a prescribed value (i.e. a full charging level of the capacitor). In other words, immediately after the write operation has shifted to the reproducing operation, the integrating circuit 8 starts the integrating operation at a low voltage. There may be a long delay to obtain the proper level of the threshold signal TH.
The normal threshold signal TH may not be output in some cases when the data reproducing operation is started immediately after the write operation. Therefore, when a read signal is turned to pulses using the low voltage level threshold signal TH in the binarization circuit 5, false pulses are generated and the possibility for generating data error becomes high.
To solve these defects, it is considered to make a time constant of the integrating circuit 8 small. However, even when a time constant is made small, the level of threshold signal TH is fluctuated by noises and the operation of the binarization circuit 5 becomes unstable.